Trusted Certification
TRUSTED-V Certification
A RISC-V-native certification programme covering the full stack, from physical silicon to the application layer. Tests run on real hardware. Scores are published and independently verifiable.
Primary action: Request an evaluation Secondary action: View the public registry
Why it exists
RISC-V is open, which is its strength and its problem. Two chips can both claim compliance and behave differently in production.
Today a buyer has no straightforward way to answer three questions:
- Does this silicon actually do what the datasheet says, on hardware, not in simulation
- Is the software stack above it safe to ship
- How does it compare against an alternative part, measured the same way
TRUSTED-V Certification answers all three with one score, one method, and public evidence.
What gets certified
Physical Silicon. ISA compliance measured on the die, memory subsystem behaviour, security primitives, thermal and power characteristics underload.
Individual IP blocks. Cryptographic cores, DMA, interrupt fabric, bus matrix, analog and mixed-signal interfaces.
The hardware abstraction layer and drivers. Register-level correctness, API conformance, memory safety, and portability across supported parts.
Middleware stacks. Protocol and interface conformance, security posture, licence provenance, integration and benchmark results.
The application layer. End-to-end use-case correctness, performance under real workloads, and security at the application boundary.
How it is tested
On-chip test suite Every test executes on real silicon, not in simulation. Four tiers: ISA compliance, system integration, functional blocks, and full-stack application behaviour.
Simulation and toolchain Multi-environment simulation behind a single unified interface, with a complete compiler toolchain across all ratified RISC-V profiles.
Supported environments: Spike, QEMU, Renode Compilers: GCC, LLVM and Clang
How it is scored
One composite score, produced automatically by the TRUSTED-V rating engine. The method is fixed, published, and reproducible by any third party holding the evidence bundle.
Correctness, 35 percent Conformance to specification. Functional behaviour at normal and boundary conditions.
Security, 30 percent Cryptographic correctness, boot chain integrity, memory safety, fault and side-channel resistance.
Performance, 20 percent Throughput, latency, determinism, and resource footprint against declared targets.
Reliability, 15 percent Stability under sustained stress, error recovery, and behaviour across thermal and voltage margins
Who it is for
- Core and chip vendors proving their part behaves as specified, with a number a customer can check
- OEMs and system integrators comparing candidate parts on identical criteria before committing to a design
- Regulated industries needing an auditable evidence trail as an input to safety and security certification