Trusted Certification
TRUSTED-V Certification
TRUSTED-V Verified is the only RISC-V-native certification covering the complete stack from physical silicon through application-layer with automated on-chip test execution and transparent open scoring.
Testing Utility
TVOTS - On-Chip Test Suite
Executed on real silicon, not simulation. Four tiers covering ISA compliance, system integration, functional blocks, and full-stack application testing.
Simulator & Compiler
RISC-V Simulator & Compiler
Multi-environment simulation with a standardised unified interface. Full compiler toolchain supporting GCC and LLVM/Clang for all ratified RISC-V profiles.
· Spike ISA
· QEMU
· Renode
· GCC + LLVM
Five Independent Certification Layers
Physical silicon ISA compliance, memory, security primitives, thermal/power
Individual IP blocks — crypto core, DMA, interrupt fabric, bus matrix, analog
Individual IP blocks — crypto core, DMA, interrupt fabric, bus matrix, analog
Middleware license, security, interface compliance, integration & benchmark
Application layer correctness, performance, security, end-to-end use cases
Scoring Methodology
Four-dimension composite score calculated automatically by the TRusteD-V Rating Engine. Fully transparent and independently verifiable.
35%
Correctness
30%
Security
20%
Performance
15%
Reliability